1. Field of the Invention
This invention relates to operational amplifier circuits and, more particularly, to improvements in the speed of the differential input stage for an operational amplifier.
2. Prior Art
To increase the slew rate of an operational amplifier while maintaining a fixed unity gain-bandwidth product, g.sub.m can be reduced by using emitter resistors in the input stage to provide emitter degeneration. The emitter resistors reduce the g.sub.m of the amplifier and provide better slew-rate and pulse response. A disadvantage of using emitter degeneration in the input stage is the degradation of the DC performance of the amplifier resulting in lower gain, lower common mode rejection ratio (CMRR), lower power supply rejection ratio (PSRR), and high offset voltage (Vos).
Emitter degeneration can be used along with matched DC current sources so that no DC current flows through the emitter resistor. This provides reduced g.sub.m and improved DC performance, but two matched DC current sources are required, and increased tub capacitance becomes a problem.
FIG. 1 shows a circuit diagram of a basic, prior-art operational amplifier circuit 100. The operational amplifier is a differential amplifier which has two input signal voltages and which provides an output voltage which is proportional to the difference between the two input signal voltages. A differential input stage 102 for this amplifier circuit includes a pair of PNP transistors. The first PNP transistor 104 has a base terminal 105, and emitter terminal 106, and a collector terminal 107. The second PNP transistor 108 has a base terminal 109, and emitter terminal 110, and a collector terminal 111. A differential input voltage V.sub.in is applied between the base terminals 105, 109. The emitter terminal 106 has one end of an emitter resistor 112 connected thereto. The other end of the emitter resistor 112 is connected to the output terminal 114 of a constant current source 116. The input terminal 118 of the constant current source 116 is connected to a +Vcc supply voltage. The value of the current from the constant current source 116 is represented as I.sub.t. The emitter terminal 110 has one end of another emitter resistor 120 connected thereto. The other end of the emitter resistor 120 is connected to the output terminal 114 of the constant current source 116.
The collector loads for the PNP transistors of the differential input stage 102 are respective transistors of a diode-transistor current mirror circuit 122 formed with a first diode-connected NPN transistor 124 and a second NPN transistor 126. The collector terminal 107 of the first PNP transistor 104 is connected to the collector terminal 128 and the base terminal of the diode-connected NPN transistor 124, which are tied together. The emitter terminal 132 of the diode-connected NPN transistor 124 is connected to a ground voltage terminal 134. The collector terminal 111 of the second PNP transistor 108 is connected to the collector terminal 138 of the NPN transistor 126. The base terminal 138 of the NPN transistor 126 is connected to the base terminal 130 of the NPN transistor 104. The emitter terminal 140 of the NPN transistor 126 is connected to the ground voltage terminal 134.
An output amplifier stage 142 has its input terminal 144 connected to the collector terminal 136 of the NPN transistor 126. An output voltage signal V.sub.out is provided at the output terminal 146 of the output amplifier 142. A compensation capacitor C.sub.c represents the capacitance between the input terminal 144 and the output terminal 146 of the amplifier 142.
The slew rate of the operational amplifier circuit 100 is the internally-limited rate of change in output voltage when a large-amplitude step function is applied to the input terminal of an operational amplifier. Slew rate is equal to I.sub.t /C.sub.c.
The unity gain-bandwidth product is the frequency range from DC to the frequency where the open-loop gain of an operational amplifier rolls off to a value of one. Unity gain-bandwidth product is approximately g.sub.m /C.sub.c.
To increase the slew rate for a fixed unity gain-bandwidth product, g.sub.m is reduced by the using the emitter resistors 112, 120. The emitter resistors 112, 120 provide emitter degeneration which reduces g.sub.m and provides better slew-rate and pulse response. The disadvantage of using emitter degeneration as shown in FIG. 1 is the reduction in DC performance by providing lower gain, lower common mode rejection ratio (CMRR), lower power supply rejection ratio (PSRR), and higher DC offset voltage (Vos).
FIG. 2 illustrates a typical prior-art operational amplifier circuit 200 which provides reduced g.sub.m but with better DC performance than the circuit of FIG. 1. A differential input stage 202 for this amplifier includes a pair of NPN transistors. The first NPN transistor 204 has a base terminal 205, and emitter terminal 206, and a collector terminal 207. The second NPN transistor 208 has a base terminal 209, an emitter terminal 210, and a collector terminal 211. A differential input voltage V.sub.in is applied between the base terminals 205, 209. An emitter resistor 212 is connected between the emitter terminal 206 and the emitter terminal 210. A first constant current source 214 has its input terminal 216 connected to the emitter terminal 206 and its output terminal 218 connected to a ground voltage terminal 220. A second constant current source 222 has its input terminal 224 connected to the emitter terminal 210 and its output terminal 226 connected to the ground voltage terminal 220. The collector terminals 207, 211 are connected to the input terminals of a current mirror circuit 228.
This circuit has reduced g.sub.m with improved DC performance. No DC current flows through the emitter resistor 212, but two matched DC current sources 214, 222 are required, and the differential pair needs to drive the two tub capacitances of the current sources 214 and 222.
FIG. 3 shows a circuit diagram of another prior-art operational amplifier 300 having improved slew rate. A differential input stage 302 includes a pair of PNP transistors and a pair of NPN transistors. The first PNP transistor 306 has a base terminal 307, an emitter terminal 308, and a collector terminal 309. The second PNP transistor 310 has a base terminal 311, an emitter terminal 312, and a collector terminal 313. A differential input voltage V.sub.in is applied between input terminals 305, 314, which are connected to respective base terminals 307, 311. The emitter terminal 306 has one end of an emitter resistor 316 connected thereto. The other end of the emitter resistor 316 is connected to the output terminal 318 of a constant current source 320. The input terminal 322 of the constant current source 320 is connected to a +Vcc supply voltage. The value of the current from the constant current source 320 is represented as I.sub.t. The emitter terminal 312 has one end of another emitter resistor 324 connected thereto. The other end of the emitter resistor 324 is connected to the output terminal 318 of the constant current source 320. The collector terminal 309 of the PNP transistor 306 is connected to a -Vcc supply voltage.
The first NPN transistor 336 has a base terminal 337, an emitter terminal 338, and a collector terminal 339. The second NPN transistor 340 has a base terminal 341, an emitter terminal 342, and a collector terminal 343. The input terminals 305, 314, to which the differential input voltage V.sub.in is applied, are also connected to respective base terminals 337, 341. The emitter terminal 338 has one end of an emitter resistor 344 connected thereto. The other end of the emitter resistor 344 is connected to the input terminal 346 of a constant current source 348. The output terminal 350 of the constant current source 348 is connected to a -Vcc supply voltage. The value of the current from the constant current source 348 is represented as I.sub.t. The emitter terminal 342 has one end of another emitter resistor 354 connected thereto. The other end of the emitter resistor 354 is connected to the input terminal 346 of the constant current source 348. The collector terminal 339 of the NPN transistor 336 is connected to a +Vcc supply voltage.
The collector terminal 313 of the PNP transistor 310 is connected to the current input terminal 360 of a bottom current mirror circuit 362. The bottom current mirror circuit 362 has a voltage supply terminal 364 which is connected to the -Vcc supply voltage. The collector terminal 343 of the NPN transistor 340 is connected to the current input terminal 366 of a top current mirror circuit 368. The top current mirror circuit 368 has a voltage supply terminal 370 which is connected to the +Vcc supply voltage.
The current output terminal 372 of the top current mirror circuit 368 and the current output terminal 374 of the bottom current mirror circuit 362 are both connected to the input terminal of the output buffer amplifier 378, which has an output terminal 380.
In contrast to the performance of the circuit of FIG. 1, the slew rate for the circuit of FIG. 3 is twice that of FIG. 1, or 2. The two current sources 320, 348 limit the slew rate.
FIG. 4 shows a circuit diagram of a prior-art operational amplifier 400. A differential emitter-follower input stage includes a pair 402 of PNP-NPN emitter-follower transistors and a pair 404 of NPN-PNP emitter follower transistors.
The pair 402 of PNP-NPN transistors includes a first PNP transistor 406 which has its collector terminal 407 connected to a negative voltage supply. Its base terminal 408 is connected to one differential input terminal 409 of the amplifier 400. Its emitter terminal 410 connected to the output terminal 411 of a constant current source 412. The input terminal 413 of the constant current source 412 is connected to a positive voltage supply. The emitter terminal 411 is also connected to the base terminal 414 of an NPN transistor 415. The collector terminal 416 is also connected to the positive voltage supply. The emitter terminal 417 is connected to one terminal 418 of an emitter resister 419.
The pair 402 of PNP-NPN transistors includes a second PNP transistor 420 which has its collector terminal 421 connected to the negative voltage supply. Its base terminal 422 is connected to the other differential input terminal 423 of the amplifier 400. Its emitter terminal 424 is connected to the output terminal of a constant current source 425. The input terminal 426 of the constant current source 425 is connected to the positive voltage supply. The emitter terminal 424 is also connected to the base terminal 427 of an NPN transistor 428. The emitter terminal 429 is connected to the other terminal 430 of the emitter resistor 419.
The collector terminal 431 is connected to an input current terminal 432 of a top current mirror circuit 433. The top current mirror circuit 433 has an output current terminal 434 which is connected to the input terminal 435 of an output buffer amplifier 436 having an output terminal 437.
In a similar manner, the pair 404 of NPN-PNP transistors includes a first NPN transistor 456 which has its collector terminal 457 connected to a positive voltage supply. Its base terminal 458 is connected to the one differential input terminal 409 of the amplifier 400. Its emitter terminal 460 is connected to the input terminal 461 of a constant current source 462. The output terminal 463 of the constant current source 462 is connected to a negative voltage supply. The emitter terminal 461 is also connected to the base terminal 464 of an PNP transistor 465. The collector terminal 466 is also connected to the negative voltage supply. The emitter terminal 467 is connected to the one terminal 418 of an emitter resister 419.
The pair 404 of NPN-PNP transistors includes a second NPN transistor 470 which has its collector terminal 471 connected to the positive voltage supply. Its base terminal 472 is connected to the other differential input terminal 423 of the amplifier 400. Its emitter terminal 474 is connected to the input terminal of a constant current source 475. The output terminal 476 of the constant current source 475 is connected to the negative voltage supply. The emitter terminal 474 is also connected to the gate terminal 477 of an PNP transistor 478. The emitter terminal 479 is connected to the other terminal 430 of the emitter resistor 419.
The collector terminal 481 is connected to an input current terminal 482 of a bottom current mirror circuit 483. The bottom current mirror circuit 483 has an output current terminal 484 which is connected to the input terminal 435 of the output buffer amplifier 436.
One problem with this type of amplifier is that it requires DC-balancing by adjustment of the four constant current sources 412, 425, 462, 475. The V.sub.BE voltage drops across the PNP and the NPN transistors are also slightly different and need to be matched to get a low Vos.